Research

FPGA implementations of neural network controllers for power electronic converters: efficient arithmetic, activation functions, and deterministic links between FPGAs and microcontrollers.

Experience

Graduate Research Assistant

2025 – Present

University of Nevada, Reno

Doctoral research on neural network-based control architectures for power electronic converters implemented on FPGAs.
Designed and validated a 32-bit full-duplex SPI interface between a TI TMS320F28335 MCU and an Altera Cyclone V FPGA with a handshake-based clock-domain-crossing architecture: error-free transfer at 9.375 MHz (7.64 Mbps) and ≈21.9 µs deterministic end-to-end latency with an RNN inverter controller.
Designed, synthesized, and validated a resource- and power-efficient segmented Chebyshev tanh activation function in single-precision floating-point arithmetic on an Altera Cyclone V FPGA.
Supported literature reviews, data collection, and preparation of proposals and journal and conference papers.

Graduate Research Assistant

Feb 2023 – Aug 2023

Texas A&M University–Kingsville, Kingsville, TX

Research on FPGA-based hardware for recurrent neural network controllers for power electronic converters.
Designed, simulated, and tested a floating-point integral block in VHDL for a neural network-based power converter controller.
Optimized a hyperbolic tangent activation function for resource usage and latency on an Intel Altera DE1-SoC FPGA.
Implemented the McBSP serial transfer protocol between a TI TMS320F28335 DSP and an Intel Altera DE1-SoC FPGA.

Graduate Mentor, NSF Research Experience for Undergraduates (REU)

Summer 2025 & Summer 2026

University of Nevada, Reno

Mentored undergraduate students in designing (Altium, KiCad) and fabricating (Voltera V-One PCB printer) a custom power inverter controller board.
Guided a student in deriving the theoretical error bound of the Chebyshev tanh approximation and of the full RNN.

Publications

Journal articles

P. Vangala, X. Fu, C. Hingu, and M. Hosur, “32-bit SPI interface design between Texas Instruments MCU and Intel FPGA enabling real-time intelligent control applications,” e-Prime – Nexus of Electrical, Electronic, and Intelligent Engineering, Art. no. 201246, 2026, doi: 10.1016/j.eprime.2026.201246.
C. Hingu, X. Fu, P. Vangala, and S. Li, “High accuracy power aware Chebyshev-based hardware implementation of tanh function for RNN controllers,” IEEE Trans. Sustain. Comput., vol. 11, no. 3, pp. 342–349, May–Jun. 2026, doi: 10.1109/TSUSC.2026.3677313.
C. Hingu, X. Fu, P. Vangala, and R. Hu, “High accuracy power optimized FPGA implementation for GELU function: A Chebyshev approach,” Electronics, vol. 15, no. 14, Art. no. 2981, 2026, doi: 10.3390/electronics15142981.
C. Hingu, X. Fu, P. Vangala, R. Mishan, and P. Fajri, “32-bit fixed and floating-point hardware implementation for enhanced inverter control: Leveraging FPGA in recurrent neural network applications,” IEEE Access, vol. 12, 2024, doi: 10.1109/ACCESS.2024.3441512.

Under review

P. Vangala, X. Fu, C. Hingu, and M. Hosur, “A resource- and power-efficient FPGA implementation of a segmented Chebyshev tanh activation function using single-precision floating-point arithmetic,” Electronics, Sep. 2026.